Generation of Testcases from UML Sequence Diagram and Detecting Deadlocks using Loop Detection Algorithm

Authors

  • Amitashree Mallick School of Computer Engineering, KIIT University, India
  • Namita Panda School of Computer Engineering, KIIT University, India
  • Arup Abhinna Acharya School of Computer Engineering, KIIT University, India

Keywords:

Software testing, Test cases, Sequence diagram, Concurrency, Deadlock

Abstract

In an environment where processes those execute concurrently, speeding up their computation is important. Deadlock is a major issue that occurs during concurrent execution. In this paper, we present an approach to generate testcases from UML sequence diagram for detecting deadlocks during the design phase. This will reduce the effort and cost involved to fix deadlocks at a later stage. Our work begins with design of sequence diagram for the system, then converting it to intermediate graph where deadlock points are marked and then traverse to get testcases. The testcases thus generated are suitable for detecting deadlocks.

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Published

2014-03-31

How to Cite

[1]
A. Mallick, N. Panda, and A. A. Acharya, “Generation of Testcases from UML Sequence Diagram and Detecting Deadlocks using Loop Detection Algorithm”, Int. J. Comp. Sci. Eng., vol. 2, no. 3, pp. 199–203, Mar. 2014.

Issue

Vol. 2 No. 3 (2014): IJCSE March Edition

Section

Research Article

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