A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology

Authors

  • Kahrari Z Department of Computer Engineering Ashtian Branch Islamic Azad University, Ashtian, Markazi, Iran
  • Karimi G Faculty of Engineering, Electrical Engineering Department, Razi University, Kermanshah

Keywords:

Trans-Impedance Amplifier, Resistive-Capacitive Feedback, Inductor Less, Low Noise, Low Power

Abstract

A low power and high speed Full adder circuit design using a new CMOS domino logic family is presented in this paper. Compared to static CMOS logic circuits, dynamic logic circuits are important as it provides better speed and has less transistor requirement. The proposed circuit has very low dynamic power consumption and less delay compared to the recently proposed circuit techniques for the dynamic logic styles. Moreover, it will be shown that the proposed circuit is extremely fault tolerant. The monte carlo simulation is performed to emphasis the fault tolerance of proposed full adder. The proposed full adder is simulated using standard 0.18 um CMOS technology.

References

J.M. Rabaey, A. Chandrakasan and B. Nikolic, (2002) Digital Integrated Circuits: A Design perspective 2e NJ:Prentice-Hall, Upper saddle River,.

S. Mathew, M. Anders, R. Krishnamurthy and S. Borkar, "A 4 GHz 130nm address generation unit with 32-bit sparse-tree adder core", IEEE J. Solid State Circuits Vol.38 (5) 2003, 689-695.

R.K. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B. Chatterjee, M. Sachdev and S. Borkar, "Dual Supply voltage clocking for 5GHz 130nm integer execution core", proceedings of IEEE VLSI Circuits Symposium, Honolulu Jun. 2002, 128-129.

S. vangal, Y. Hoskote, D. Somasekhar, V. Erraguntla, J. Howard, G. Ruhl, V. Veeramachaneni, D. Finan, S. Mathew, and N. Borkar, "A 5-GHz floating point multiply accumulator in 90-nm dual VT CMOS", in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, Feb.2003, 334–335.

V. Navarro-Botello, J. A. Montiel-Nelson, and S. Nooshabadi, "Analysis of high performance fast feedthrough logic families in CMOS", IEEE Trans. Cir. & syst. II, vol. 54, no. 6, Jun. 2007, 489- 493.

N. Srinivasa Gupta, M. Satyanarayana, “A Novel Domino Logic for Arithmetic Circuits” International Journal of Innovative Technology and Exploring Engineering, Volume-3, Issue-3, August 2013.

Jehangir Rashid Dar, Sajad Ahmad Ganiee, “Novel Low-Power, Energy-Efficient Full Adder for Ultra Deep-Submicron Technology” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 3, Issue 3, March 2014.

Chip-Hong Chang; Jiangmin Gu; Mingyan Zhang; , "A review of 0.18µm adder performance for tree structured arithmetic circuits” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.13no.6, pp. 686- 695, June 2005.

Goel, S.; Kumar, A.; Bayoumi, M. A.; , "Design of Robust, Energy-Efficient Full Adders for Deep-Sub micrometer Design Using HybridCMOS Logic Style," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.14, no.12, pp.1309-1321, Dec. 2006.

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Published

2025-11-11

How to Cite

[1]
Z. Kahrari and G. Karimi, “A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology”, Int. J. Comp. Sci. Eng., vol. 4, no. 1, pp. 14–16, Nov. 2025.

Issue

Vol. 4 No. 1 (2016): IJCSE January Edition

Section

Research Article

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