Design and Implementation of Adiabatic Sequential and Combinational circuits using Reversible Gate

Authors

  • Yadav B Dept. of Electronics and Communication, LNCT, Bhopal
  • Varma T Dept. of Electronics and Communication, LNCT, Bhopal

DOI:

https://doi.org/10.26438/ijcse/v7i10.251255

Keywords:

Reversible Gates, 4-bit Adder/ Sub tractor, Garbage Output, Quantum Cost

Abstract

Programmable reversible logic circuit (RLC) is design style for nanotechnology and quantum computing with minimum heat generation, quantum cost and garbage output. Late advances in reversible rationale utilizing and quantum PC calculations consider enhanced PC engineering and math rationale unit plans. In this paper, we survey the N-bit reversible logic adder and sub tractors are used with minimal delay, and may be configured to produce a variety of logical calculations. The reversible N-bit adder/ sub tractor design is verified and its advantages over the only existing adder design are quantitatively analyzed.

References

[1] Nicolas Jeanniot, Gaël Pillonnet, Pascal Nouet, Nadine Azemard and Aida Todri-Sanial, “Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic”, 978-1-5386-1553-9/17/$31.00 ©2017 IEEE.

[2] Sachin Maheshwari, V.A.Bartlett and Izzet Kale, “Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers”, 978-1-5386-3974-0/17/$31.00 ©2017 IEEE.

[3] Gopi Chand Naguboina and K. Anusudha, “Design and Synthesis of Combinational Circuits Using Reversible Decoder in Xilinx”, IEEE International Conference on Computer, Communication, and Signal Processing (ICCCSP-2017).

[4] Marcin Bryk, Kryszt Gracki, Pawal Kerntop and Marek Pawlowski, “Encryption using reconfigurable reversible logic gate and its simulation in FPGAs”, Mixed Design of Integrated Circuits and Systems, 2016 MIXDES - 23rd International Conference IEEE Xplore: 04 August 2016.

[5] Umeshkumar, LavishaSahu, Uma Sharma, “Performance Evaluation of Reversible Logic Gates”, International Conference on ICT in Business Industry & Government (ICTBIG), IEEE 2016.

[6] Lafifa Jamal and Hafiz Md. HasanBabu, “Design and Implementation of a Reversible Central Processing Unit”, IEEE Computer Society Annual Symposium on VLSI, 2015.

[7] Junchaw Wing and Ken Choi, “A Carry look ahead adder designed by reversible logic”, SOC Design Conference (ISOCC), International Conference on IEEE 2015.

[8] D. Grobe, R. Wille, G.W. Dueck, and R. Drechsler, “Exact multiple control Toffoli network synthesis with sat techniques”, IEEE Transaction on CAD, 2014.

[9] Sachin Maheshwari, V.A.Bartlett and Izzet Kale, “4-phase resettable quasi-adiabatic flip-flops and sequential circuit design”, 978-1-5090-0493-5/16/$31.00 ©2016 IEEE.

[10] D.Jothi and R.Sivakumar, “A Completely Efficient Charge Recovery Adiabatic Logic Content Addressable Memory”, 2015 International Conference on Computers, Communications, and Systems.

[11] Krishna Murthy, Gayatri G, Manoj Kumar “Design of Efficient Adder Circuits Using Proposed Parity Preserving Gate” VLSICS Vol.3, No.3, June 2012.

[12] Jayashree H V and Ashwin S, “Berger Check and Fault Tolerant Reversible Arithmetic Component Design”, 978-1- 4799 - 8364-3/ 15/ $31.00 @ 2015 IEEE.

Downloads

Published

2019-10-31
CITATION
DOI: 10.26438/ijcse/v7i10.251255
Published: 2019-10-31

How to Cite

[1]
B. Yadav and T. Varma, “Design and Implementation of Adiabatic Sequential and Combinational circuits using Reversible Gate”, Int. J. Comp. Sci. Eng., vol. 7, no. 10, pp. 251–255, Oct. 2019.