Improved stability and access time Using Different 6T SRAM Cells at Low Voltage
DOI:
https://doi.org/10.26438/ijcse/v7i7.298301Keywords:
ADSE, FinFET, High-k spacer SRAM, UnderlapAbstract
Contradictory nature of read and write stability and stability with speed necessitates the use of FinFET device which has less statistical variability, sensitivity and more on current. In this work, we explored three different FinFET device structures. These structures are used to form three different 6T SRAM cells. All the simulations are done with the help of Sentaurus TCAD. Three SRAM cells are compared to reduce access time and enhance data stability. We found that ADSE FinFET SRAM achieve significant improvement in access time as compared to Underlap FinFET SRAM cell without degradation of cell stability. On the other hand High-k spacer SRAM cell shows noteworthy increase in stability over other two cells with somewhat slower response.
References
[1]. Jawar Singh, Saraju P.Mohanty, Dhiraj K. Pradhan, “Robust SRAM Designs and Analysis,” Available at www.springer.com, 2013
[2]. J. J. Kim et al., “Relaxing Conflict Between Read Stability and Writ ability in 6T SRAM Cell Using Asymmetric Transistors,” IEEE EDL, vol. 30, no. 8, pp. 852-854, August 2009.
[3]. V. A. A. Goud et al, “Atomistic Tight-Binding Based Evaluation of Impact of Gate Underlap on Source to Drain Tunneling in 5nm Gate Length Si FinFETs,” IEEE DRC, p. 51,52, June 2013.
[4]. V. Trivedi, J. G. Fossum, and M. M. Chowdhury, “Nanoscale FinFETs with gate–source/drain underlaps,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 56–62, Jan. 2005.
[5]. FinFET from Device to Architecture 2014 (online) Available: http://dx.doi.org/10.1155/2014/365689
[6]. Pankaj Kumar Pal, Shivam verma, B.K.kaushik, “Statistical variability and sensitivity Analysis of dual-k spacer FinFET,” IEEE Trans. On electronic devices and solid state circuits, 2015.
[7]. D. Pham, L. Larson, and J.-W. Yang, “FinFET device junction formation Challenges,” in Proc. Int. Workshop Junction Technol., May 2006, pp. 73–77.
[8]. C. R. Manoj and V. R. Rao, “Impact of high-κ gate dielectrics on the device and circuit performance of nanoscale FinFETs,” IEEE Electron Device Lett., vol. 28, no. 4, pp. 295–297, Apr. 2007.
[9]. P.K.Pal, B.K.Kaushik, and S.Dasgupta “Investigation of symmetric dual k spacer trigate FinFET from delay perspective,” IEEE Trans. on Electron Devices,” vol.61, no.11, pp-3579-3585, Nov.2014.
[10]. J.P.colinge, FinFET and Other Multi Gate Transistor, a series on Integrated Circuits and Systems,” Springer.com” August 2007
[11]. Sherif A. Tawfik, Zhiyu Liu, and Volkan Kursun, “ Independent gate and Tied – Gate FinFET SRAM circuits,” IEEE ICM - December 2007.
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