Performance Analysis of Array Multipliers Using Different Logic Configurations
DOI:
https://doi.org/10.26438/ijcse/v7i6.303306Keywords:
Multiplier, CMOS Logic, Pseudo-NMOS Logic, Transmission Gate Logic, Power, DelayAbstract
Power and speed are the two important design aspects that impact the designing of any circuits. One of the most widely used arithmetic operation in digital circuits is Multiplication. There are different Multipliers designed depending on the speed and the hardware. There are different technologies with different features. In this paper 4- bit and 8- bit Array Multipliers are been designed using different designing techniques. The Multipliers are designed using CMOS Logic Configuration, Pseudo-NMOS Logic Configuration and Transmission gate Logic Configuration and are compared in terms of Power and delay. The Power Delay Product (PDP) gives the overall performance of the Multipliers.
References
[1] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, Low power CMOS digital design, IEEE J. Solid-State Circuits, vol. 27, pp. 473–484, 1992.
[2] W. Al-Assadi, A. P. Jayasumana, and Y. K. Malaiya, Pass-transistor logic design,ǁ Int. J. Electron., vol. 70, pp. 739–749, 1991.
[3] I. S. A. Khater, A. Bellaouar, and M. I. Elmastry, Circuit techniques for CMOS low power high-performance multipliers, IEEE J. Solid-State Circuits, vol. 31, pp. 1535–1546, 1996.
[4] K. Yano, Y. Sasaki, K. Rikino, and K. Seki, Top down pass transistor logic design, IEEE J. Solid State Circuits, vol. 31, pp. 792 – 803, 1996.
[5]R. Zimmermann and W. Fichtner, Low power logic styles: CMOS versus pass transistor logic, IEEE J. Solid State Circuits, vol. 32, pp. 1079– 1090, 1997.
[6] T. Sakurai, Closed form expressions for interconnection delay, coupling, and crosstalk in VLSI‘s, IEEE Trans Electron Devices, vol. 40, pp. 118–124, 1993.
[7]V. Adler and E. G. Friedman, Delay and power expressions for a CMOS inverter driving a resistive capacitive load, Analog Integrated Circuits Signal Processing, vol. 14, pp. 29–39, 1997.
[8] A. Morgensh tein, A. Fish and I. A. Wagner, Gate Diffusion Input (GDI) A power efficient method for digital combinatorial circuits, IEEE Transactions on VLSI systems, vol.10, pp. 566-581, 2002.
[9] D. Wang, M. Yang, W. Cheng, X. Guan, Z. Zhu, Y. Yang Novel Low Power Full Adder Cells in 180nm CMOS Technology Industrial Electronics and Applications, pp 430-433, 2009.
[10]P. C. H. Meier, Analysis and Design of Low Power Digital Multipliers, Ph.D. Thesis, Carnegie Mellon University, Dept. of Electrical and Computer Engineering, Pittsburgh, Pennsylvania, 1999.
[11] WALLACE, C.S., A SUGGESTION FOR A FAST MULTIPLIER, IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, EC-13, PP. 14-17, 1964.
[12] A. P. CHANDRAKASAN, S. SHENG AND R. W. BORDERSEN, LOW POWER CMOS DIGITAL DESIGN, IEEE J. SOLID STATE CIRCUITS, VOL. 27, PP. 473–484, 1992.
[13] N. RAVI, A. SATISH, T. J. PRASAD AND T. S. RAO, A NEW DESIGN FOR ARRAY MULTIPLIER WITH TRADE OFF IN POWER AND AREA, VOL. 8, PP. 533-537, 2011
[14] N. ANUAR, Y. TAKAHASHI AND T. SEKINE, 4×4-BIT ARRAY TWO PHASE CLOCKED ADIABATIC STATIC CMOS LOGIC MULTIPLIER WITH NEW XOR 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM ON CHIP, PP. 364- 368, 2010.
[15]S. DEVADAS AND S. MALIK, A SURVEY OF OPTIMIZATION TECHNIQUES TARGETING LOW POWER VLSI CIRCUITS, IN PROC. 32ND ACM/IEEE DESIGN AUTOMATION CONF., PP. 242–247, 1995.
[16] F. AZNAR, W. GABERL, AND H. ZIMMERMANN, “A HIGHLY SENSITIVE 2.5 GB/S TRANSIMPEDANCE AMPLIFIER IN CMOS TECHNOLOGY,” IN IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, PP. 189 – 192, (2009).
Downloads
Published
How to Cite
Issue
Section
License
This work is licensed under a Creative Commons Attribution 4.0 International License.
Authors contributing to this journal agree to publish their articles under the Creative Commons Attribution 4.0 International License, allowing third parties to share their work (copy, distribute, transmit) and to adapt it, under the condition that the authors are given credit and that in the event of reuse or distribution, the terms of this license are made clear.
