Design and Simulation of Two – bit Multiplier Circuit using MGDI Technique
DOI:
https://doi.org/10.26438/ijcse/v7i6.5661Keywords:
CPL, DSCH 3.5, Karnaugh’ map, Multiplier, PTL, Shannon’s Expansion TheoremAbstract
Multiplier in Digital Signal Processing (DSP) and Elliptic Curve Cryptography (ECC) are crucial. Thus modern DSP and ECC systems require to develop low power multiplier circuits to reduce the power dissipation and at the same time to increase the speed. One of the efficient ways to reduce power dissipation is by the use of Modified Gate Diffusion Input (MGDI) which at the same time reduces the circuit parameters like transistor count, implementation cost, space required and propagation delay. This paper proposes a new design technique for two-bit binary multiplier and hence multi-bit binary multiplier using the proposed two-bit multiplier circuit. This paper also implements the proposed two-bit multiplier using DSCH 3.5. The proposed technique claims lower power consumption, lower cost, lower space required and also lesser number of transistor than other conventional techniques like CMOS, PTL, CPL etc. A comparative study of the proposed technique has been dealt here clearly which shows the novelty of the proposed technique.
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