Implementation of SHA on FPGA

Authors

  • Anand A Computer Science, ABES Institute of Technology, Ghaziabad, UP, India
  • Praveen P Electronics & Communication, RIET, Gr.Noida, UP, India
  • Shruti Computer Science, BITS, Bhopal, MP, India

Keywords:

ASIC, Digital Signature, FPGA, Message Digest, SHA, RTL, VHDL

Abstract

In this paper, an FPGA based SHA1 core is designed and implemented using the hardware description language VHDL. Hash functions are the most important cryptographic algorithms and used in the several fields of communication integrity and signature authentication. These functions produce a fixed-size fingerprint or hash value for a variable length (very long) message. The hash function SHA-1, Secure Hash Algorithm, is examined in order to find the common constructs that can be used to implement it using hardware blocks of the FPGA. As a result, a hash core supporting SHA-1 and having a standard single bit SPI is proposed. The hardware is described using VHDL and verified on Xilinx FPGA.

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Published

2015-05-30

How to Cite

[1]
A. Anand, P. Praveen, and Shruti, “Implementation of SHA on FPGA”, Int. J. Comp. Sci. Eng., vol. 3, no. 5, pp. 252–257, May 2015.

Issue

Section

Research Article