Hardware Implementation of Fast Recursive Walsh-Hadamard Transform

Authors

  • Mazumder P Department of Electronics and Communication Engineering, Regent Education and Research Foundation, Kolkata 700121, India
  • Middya R Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700032, India
  • Naskar MK

Keywords:

Signal processing, VLSI, FFT, Transforms

Abstract

The Walsh Hadamard Transform is an extremely relevant concept in modern digital image data compression. This paper examines the feasibility of using a tensor product based approach to Walsh Hadamard Transfrom for implementation to hardware architecture using FPGA technology. This paper explains the derivation of a highly parallel and very fast algorithm for the computation of both one-dimensional and two-dimensional transforms using tensor product. Such a fast dedicated hardware design for the Walsh Hadamard Transform will help a wide range of digital signal processing applications.

References

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Published

2025-11-24

How to Cite

[1]
P. Mazumder, R. Middya, and M. K. Naskar, “Hardware Implementation of Fast Recursive Walsh-Hadamard Transform”, Int. J. Comp. Sci. Eng., vol. 7, no. 1, pp. 28–32, Nov. 2025.

Issue

Vol. 7 No. 1 (2019): IJCSE Special Issue Jan Edition

Section

Research Article

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