FPGA Implementation for Fractal Quadtree Image Compression

Authors

  • Padmavati S Dept. of ECE, Jain University, Bengaluru, India
  • Meshram V Dept. of ECE, Dayananda Sagar University, Bengaluru, India

DOI:

https://doi.org/10.26438/ijcse/v6i10.405409

Keywords:

Architecture, Fractal Image Compression, FPGA, Quadtree Decomposition

Abstract

The growth of digital technology over the past decades is leading to new challenges like storage and transmission of digital images. As the digital image in its raw form occupies more storage space and takes longer time for transmission. Several image compression methods exist to address this issue and fractal image compression is one among the popular image compression methods. But fractal image compression has a disadvantage of more encoding time. In this paper, we have proposed a new architecture for fractal image compression. The proposed architecture is modeled using Verilog HDL, synthesized using Xilinx ISE 14.2, implemented on Xilinx Spartan 6 FPGA board and is tested on Standard Lena image[512x512]. The proposed architecture will reduce the design cycle time and the implementation cost. The results of the proposed architecture have shown a considerable reduction in encoding time to 5.897ns when compared to software implementation

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Published

2025-11-17
CITATION
DOI: 10.26438/ijcse/v6i10.405409
Published: 2025-11-17

How to Cite

[1]
S. Padmavati and V. Meshram, “FPGA Implementation for Fractal Quadtree Image Compression”, Int. J. Comp. Sci. Eng., vol. 6, no. 10, pp. 405–409, Nov. 2025.

Issue

Vol. 6 No. 10 (2018): IJCSE October Edition

Section

Research Article

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