Constraint Random Verification of Network Router for System on Chip Applications Using Advanced Verification Methodologies

Authors

  • Lata shravya Bandaru ECE, JNTU HYD, India
  • Vamshi Krishna Sandepudi ECE, JNTU HYD, India
  • Chandhupatla Sindhuja ECE, JNTU HYD, India

Keywords:

Systemverilog, Ficinalcoverage, Assertions

Abstract

The focus of this Paper is the actual implementation of Network Router and verifies the functionality of the five port router for network on chip using the latest verification methodologies, Hardware Verification Languages(s) and EDA tools and qualifies the Design for Synthesis and implementation. This Router design contains Four output ports and one input port, it is packet based Protocol. This Design consists of Registers, FSM and FIFO’s. The Verification goes on it finds functional coverage of the Network Router by using System Verilog.

References

D.Chiou,“MEMOCODE2011Hardware/SoftwareCoDesignContest”,https://ramp.ece.utexas.edu/redmine/Attachments/ esignContest.pdf

Xilinx,“ML605HardwareUserGu de”, http://www.xilinx.com/support/documentation/boardsand its/ug534.pdf

Xilinx,“LogiCOREIPProcessor Local Bus (PLB) v4.6”, http://www.xilinx.com/support/documentation/ip ocumentation/plb v46.pdf

“Application Note: Using the Router Interface to Communicate Motorola, ANN91/D Rev. 1, 01/2001. Cisco Router OSPF: Design& Implementation Guide, Publisher: McGraw-Hill

“LRM”, IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language – IEEE STD 1364-199.

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Published

2014-02-28

How to Cite

[1]
L. shravya Bandaru, V. K. Sandepudi, and C. Sindhuja, “Constraint Random Verification of Network Router for System on Chip Applications Using Advanced Verification Methodologies”, Int. J. Comp. Sci. Eng., vol. 2, no. 2, pp. 6–10, Feb. 2014.

Issue

Vol. 2 No. 2 (2014): IJCSE February Edition

Section

Research Article

License

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