High Throughput Compact Delay Insensitive Asynchronous NOC Router

Abstract

The focus of this Paper is the actual implementation of Network Router and verifies the functionality of the five port router for network on chip using the latest verification methodologies, Hardware Verification Languages and EDA tools and qualifies the Design for Synthesis an implementation. This Router design contains Four output ports and one input port, it is packet based Protocol. This Design consists Registers, Fsm and FIFO’s.For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized time multiplexed approach was used. Compared to the provided software reference implementation, our direct-mapped approach achieves three orders of magnitude speedup, while our virtualized time multiplexed approach achieves one to two orders of magnitude speedup, depending on the network and router configuration.