Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach

Authors

  • P Gopi Krishna Rise Krishna Sai Gandhi Group Of Institutions
  • KV Subrahmanyam Rise Krishna Sai Gandhi Group Of Institutions
  • S Chandra Sekhar Rise Krishna Sai Gandhi Group Of Institutions

Keywords:

Adder, Decimal Arithmetic, Reversible logic, Garbage output, HNG gate

Abstract

Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, optical information processing, quantum computing and nanotechnology. This research proposes a new implementation of adder in reversible logic. The design reduces the number of gate operations compared to the existing adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay. We can use it to construct more complex systems in nanotechnology.

References

R. Landauer, "Irreversibility and Heat Generation in the Computational Process", IBM Journal of Research Development, 5, 1961, 183-191.

Bennett, C., "Logical Reversibility of Computation," IBM Journal of Research and Development, 17, 1973, 525-532.

Hafiz Md. Hasan Babu and A. R. Chowdhury, "Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-bit Parallel Adder", VLSI Design 2005, pp-255-260, Kolkata, India, Jan 2005.

Himanshu. Thapliyal, S. Kotiyal and M.B Srinivas, "Novel BCD Adders and their Reversible Logic Implementation for IEEE 754r Format", VLSI Design 2006, Hyderabad, India, Jan 4-7, 2006, pp. 387-392.

R. James, T. K. Shahana, K. P. Jacob and S. Sasi,"Improved Reversible Logic Implementation of Decimal Adder", IEEE 11th VDAT Symposium Aug 8-11, 2007.

Md. M. H. Azad Khan, "Design of Full-adder With Reversible Gates", InternationalConference on Computer and Information Technology, Bangladesh, 2002, pp. 515-519.

R. Feynman, "Quantum Mechanical Computers", Optical News, 1985, pp. 11-20.

H. Thapliyal and M.B Srinivas, "A Novel Reversible TSG Gate and Its Application forDesigning Reversible Carry Look-Ahead and Other Adder Architectures", Tenth Asia-Pacific Computer Systems Architecture Conference, Singapore, Oct 24 - 26, 2005

Rekha K.james,Shahana T.K,T.Poulose Jacob,Sreela Sasi “A new look at Reversible logic implementation of Decimal adder”,IEEE 1- 4244-1368-0/07.

Jagadguru Swami Sri Bharati Krishna Tirthaji Maharaja, Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda, Delhi (1965).

Rakshith Saligram and Rakshith T.R. "Novel Code Converter Employing Reversible Logic", International Journal of Computer Application, ,Volume 52– No.18, August 2012.

Downloads

Published

2014-10-31

How to Cite

[1]
P. Gopi Krishna, K. Subrahmanyam, and S. Chandra Sekhar, “Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach”, Int. J. Comp. Sci. Eng., vol. 2, no. 10, pp. 19–25, Oct. 2014.

Issue

Vol. 2 No. 10 (2014): IJCSE October Edition

Section

Research Article

License

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

Authors contributing to this journal agree to publish their articles under the Creative Commons Attribution 4.0 International License, allowing third parties to share their work (copy, distribute, transmit) and to adapt it, under the condition that the authors are given credit and that in the event of reuse or distribution, the terms of this license are made clear.