Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits

Authors

  • Balaji B Dept. Of Ece, Srts College,Kadapa
  • Saleem Malik S Dept. Of Ece, Srts College,Kadapa

Keywords:

Flip-Flops, High-Speed, Leakage Power, Low-Power

Abstract

In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the large capacitance present in the pre-charge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a 90 nm technology when compared to the Semi dynamic flip-flop, with no degradation in speed performance. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs.

References

J. Yuan and C. Svensson, “New single-clock CMOS latches and flipflops with improved speed and power savings,”IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 62–69, Jan. 1997.

A. Hirata, K. Nakanishi, M. Nozoe, and A. Miyoshi, “The cross chargecontrol flip-flop: A low-power and high-speed flip-flop suitable for mobile application SoCs,” inProc. Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2005, pp. 306–307.

N. Nedovic, M. Aleksic, and V. G.

Oklobdzija, “Conditional pre-charge techniques for power-efficient dual-edge clocking,” inProc. Int. Symp. Low-Power Electron. Design, 2002, pp. 56–59.

P. Zhao, T. K. Darwish, and M. A. Bayoumi, “High-performance and low-power conditional discharge flip-flop,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 477–484, May 2004.

V. Stojanovic and V. Oklobdzija,

“Comparative analysis of masterslave latches and flip-flops for high-performance and low-power systems,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536–548, Apr. 1999

J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ: PrenticeHall, 2003.

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Published

2014-09-30

How to Cite

[1]
B. Balaji and S. Saleem Malik, “Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power Cmos Vlsi Circuits”, Int. J. Comp. Sci. Eng., vol. 2, no. 9, pp. 75–77, Sep. 2014.

Issue

Vol. 2 No. 9 (2014): IJCSE September Edition

Section

Research Article

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