Reverse Conversion of Signed – Digit Number System: Fast Transformation of Sign – Magnitude Output

Authors

  • Chakraborty MS Dept. of Computer Science, Indas Mahavidyalaya, PO: Indas, Bankura (WB), India, PIN

DOI:

https://doi.org/10.26438/ijcse/v6i5.454457

Keywords:

Signed – Digit Number Systems, Reverse Conversion, Digit – Parallel Transformation, Conventional Form

Abstract

In spite of various advantages of using signed – digit number system, so far reverse conversion has remained a major performance bottleneck of signed – digit arithmetic. Yet, the sign – magnitude output algorithm(s) for reverse conversion of signed – digit number system is known to be extensible to provide radix – complement output at constant additional time. In other words, the additional delay due to the carry that may otherwise propagate once again, may be easily eliminated. This is supposed to nullify the negative aspects of reverse conversion on arithmetic units working on signed – digit number system in longer run. Thus significant performance enhancement of signed – digit number system(s) may be possible. However, as shown in this paper, the existing digit – parallel algorithm for sign – magnitude to radix – complement output transformation can not work correctly. So a modified scheme is proposed and its correctness is proved.

References

A. Avizienis, “Signed - digit number representation for fast parallel arithmetic”, IRE Transactions on Electronic Computers, Vol. 10, Issue 3, pp.389 – 400, 1961.

I. Koren, Computer Arithmetic Algorithms, 2nd ed, University Press, Oxford, 2003.

G. Smitha, A. H. Fahmy, A. P. Vinod, “Redundant Adders Consume Less Energy”, In Proceedings of IEEE APC on Circuits and Systems, Singapore, pp.422-425, 2006.

D. Crookes and M. Jiang, “Using signed - digit arithmetic for low power multiplication”, Electronics Letters, Vol. 43, No. 11, pp. 613 – 614, 2007.

D.S. Phatak, S. Kahle, H.Kim, J.Lue, “Hybrid Signed Digit Representation for Low Power Arithmetic Circuits”, In Proceddings of Low Power Workshop in Conjunction with ISCA. Barcelona, Spain, pp.1 – 7, 1998.

Y.He, C.–H. Chang, “A Power - Delay Efficient Hybrid Carry - Lookahead/ Carry - Select Based Redundant Binary to Two's Complement Converter”, IEEE Transactions on Circuits and Systems – I, Vol. 55, No.1, pp.336 – 346, 2008.

S.K. Sahoo, A. Gupta, A.R. Asati, C. Shekhar, “A Novel Redundant Binary Number to Natural Binary Number Converter”, Journal of Signal Processing Systems, Vol.59, pp.297-307, 2010.

M.S. Chakraborty, “Reverse Conversion Schemes for Signed – digit Numbers Systems: A Survey”, Journal of Institute of Engineers of India, Series B, Vol. 97, Issue 4, pp.589 – 593, 2016.

M.S. Chakraborty, A.C Mondal, “Reverse Conversion of Signed – Digit Number Systems: Transforming Radix – Complement Output”, IJEECS, Vol. 4, No. 3, pp.665 – 669, 2016.

M.S. Chakraborty, S.K. Sao, A.C. Mondal, “Equivalence of Reverse Conversion of Binary Signed-Digit Number System and Two’s-Complement to Canonical Signed-Digit Recording”, IEEE International Conference on Recent Advancement of Information Technology (RAIT), IIT (ISM), Dhanbad, India, Vol. 2, pp.662 – 666, 2018.

T. Stouraitis, and C. Chen, “Fast Digit-Parallel Conversion of Signed-Digit into Conventional Representations”, Electronics Letters, Vol. 27, Issue 11, pp.964-965, 1991.

T. Srikanthan, S.K. Lam, and M. Suman, “Area–Time Efficient Sign Detection Technique for Binary Signed–digit Number System”, IEEE Transactions on Computers, Vol.53, Issue 1, pp.69-72, 2004.

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Published

2025-11-13
CITATION
DOI: 10.26438/ijcse/v6i5.454457
Published: 2025-11-13

How to Cite

[1]
M. Chakraborty, “Reverse Conversion of Signed – Digit Number System: Fast Transformation of Sign – Magnitude Output”, Int. J. Comp. Sci. Eng., vol. 6, no. 5, pp. 454–457, Nov. 2025.

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Section

Research Article