Implementation of Low Power Digital FIR Filter Design Based on low power multipliers and adders

Authors

  • U.Venkata Sivaiah Department of ECE, Dr.S.G.I.E.T, Markapur, Andhra Pradesh, India
  • P.Prasanna murali Krishnna Department of ECE, Dr.S.G.I.E.T, Markapur, Andhra Pradesh, India
  • Y. Devaraju Department of ECE, Dr.S.G.I.E.T, Markapur, Andhra Pradesh, India

Keywords:

Low Power, Booth Multiplier, Folding Transformation

Abstract

This paper presents the methods to reduce dynamic power consumption of a digital Finite Impulse Response (FIR) filter these methods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear phase architecture and applied to fir filters to reduce power consumption due to this glitching is also reduced. The minimum power achieved is 110mw in fir filter based on shift/add multiplier in 100MHZ to 8taps and 8bits inputs and 8bits coefficients. The proposed FIR filters were synthesized implemented using Xilinx ISE Spartan 3E FPGA and power is analyzed using Xilinx XPower analyzer.

References

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Published

2013-12-30

How to Cite

[1]
U. Sivaiah, P. murali Krishnna, and Y. Devaraju, “Implementation of Low Power Digital FIR Filter Design Based on low power multipliers and adders”, Int. J. Comp. Sci. Eng., vol. 1, no. 4, pp. 23–28, Dec. 2013.

Issue

Vol. 1 No. 4 (2013): IJCSE December Edition

Section

Research Article

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