Performance Analysis of 4 FDCT Algorithms Using Hardware Synthesis and Simulation
DOI:
https://doi.org/10.26438/ijcse/v6i4.149154Keywords:
FDCTAlgorithm, Dataflow diagram, Matlab Simulink, Xilinx synthesis, Post Route Simulation, Maximum padding delay, Maximum combinational path delayAbstract
In order to find out the best fast DCT algorithms presented among numerous algorithms,four Fast DCT Algorithms which are popular and frequently used are considered in the paper. Referring their dataflow graphs 4 architectures are designed using Matlab Simulink. HDL coder is used to generate automated VHDL code. The block setsused in the Simulink design are manually modified tothe fixed point 16-bit data type. VHDL code is generated using HDL coder. The designs are synthesized using Xilinx ISE 14.5. A test bench program is written to test the 4 algorithms with the same set of data. Using the test bench program, a post route simulation up to the pin level is executed. From the timing report and synthesis report, the results are compared to find out the best FDCT algorithm in terms of hardware utilization and simulated timing performance.Loeffler’s Algorithm is performing the best, both in terms of hardware utilization and timing requirement as found from the hardware synthesis report and timing report after post route simulation.
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