FPGA Implementation of Configurable Linear Feedback Shift Register using Verilog
DOI:
https://doi.org/10.26438/ijcse/v6i4.143146Keywords:
Configurable Linear Feedback Shift Register, Field Programmable Gate Array, Verilog, Reversible Logic, Shift Register, Random Number GeneratorAbstract
The proffered paper is presented on the practical implementation of a Configurable Linear Feedback Shift Register using Verilog and assesses its various parameters with respect to its configurable aspects and physical performance. The practical implementation is configurable with respect to Number of Bits, Seed Value, Number of Taps and Tap Position that increases the randomness of the output thus creating a more pseudo-random cycle. Moreover, reversible logic is explored and analysed and the technology is comprehended in this paper as an emerging technology that can be used to implement the designed Configurable Linear Feedback Shift Register. Reversible logic is said to enhance the power efficiency of a logical circuit than the conventional models and thus eases the migration to emerging technologies of Quantum Computing, Portable Embedded Systems and Low Power VLSI. The chosen target for the hardware realization of the CLFSR is Altera Cyclone II FPGA. Furthermore, simulation and synthesis of the design is done using ModelSim-Altera for Quartus II 12.1 Web Edition.
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