Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog HDL

Authors

  • D.Venu Gopal Santhiram Engineering College, Nandyal
  • M. Mohan Reddy Santhiram Engineering College, Nandyal

Keywords:

CLAA, Delay, CSLA, Area, Array Multiplier, HDL Modeling & Simulation

Abstract

This project deals with the comparison of the VLSI design of the carry look-ahead adder (CLAA) based 32-bit unsigned integer multiplier and the VLSI design of the carry select adder (CSLA) based 32-bit unsigned integer multiplier. Both the VLSI design of multiplier multiplies two 32-bit unsigned integer values and gives a product term of 64-bit values. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation whereas in CSLA based multiplier also uses nearly the same delay time for multiplication operation the overall simulation can be observed by using model sim and the synthesis report can be given by using Xilinx ise.

References

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P. S. Mohanty, “Design and Implementation of Faster and Low Power Multipliers”, Bachelor Thesis. National Institute of Technology, Rourkela, 2009. http://ethesis.nitrkl.ac.in/213/1/10509019_final.pdf.pdf.

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Published

2014-05-31

How to Cite

[1]
D. Gopal and M. M. Reddy, “Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog HDL”, Int. J. Comp. Sci. Eng., vol. 2, no. 5, pp. 29–31, May 2014.

Issue

Vol. 2 No. 5 (2014): IJCSE May Edition

Section

Research Article

License

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