A Comparative Study of Full Adder Using Different Logic Style

Authors

  • Sarkar E Department of Electronics & Communication, MCKV Institute of Engineering, Liluah Howrah
  • Giri Tunga S Department of Electronics & Communication, Pailan College of Management & Technology, Kolkata
  • Samanta A Department of Electronics & Communication, Pailan College of Management & Technology, Kolkata

Keywords:

Full Adder, CMOS, Transmission Gate (TG), Pass Transistor, Power Dissipation, Delay, PDP

Abstract

In recent year, power dissipation is one of the biggest challenges in VLSI design. Adder circuits are the main sources of power dissipation in signal processing units. By reducing the number of transistors in the circuits and the design structures are may occupied small area and low power design. In this paper a Full Adder Circuit is designed by using CMOS, Transmission gates and pass Transistor logic and the power and delay are analysed. Power consumption and speed are two important but conflicting design aspects; hence a better way to evaluate circuit performance is power delay product (PDP). The designs are implemented and power, delay results are obtained by using TANNER EDA Tool. The results show that the transistor counts, delay and the power required are significantly concentrated in the design.

References

Sung-Mo Kang and Yusuf Leblebici; “CMOS digital integrated circuits: analysis and design”; Tata Mcgraw-Hill, Third Edition, 2003

Kaushik Roy and S.C.Prasad, “Low power CMOS VLSI circuit design”, Wiley, 2000.

Debika Chaudhuri, Atanu Nag, Sukanta Bose; “Low Power Full Adder Circuit Implemented In Different Logic”; IJIRSET, Volume3, Special Issue 6, February 2014

D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” IEEE Proc. Circuits Devices Syst., vol. 148, no. 1, pp. 19–24, Feb. 2001.

Vahid Foroutan and Keivan Navi, “Low Power Dynamic CMOS Full-Adder Cell”; IJCSIT, Vol.6(3), 2015

Nishan Singh, Mandeep Kaur, Amardeep singh, Puneet Jain, “An Efficient Full Adder Design using Different Logic Styles”; IJCA, Volume 98 – No.21, July 2014

Downloads

Published

2025-11-11

How to Cite

[1]
E. Sarkar, S. Giri Tunga, and A. Samanta, “A Comparative Study of Full Adder Using Different Logic Style”, Int. J. Comp. Sci. Eng., vol. 4, no. 6, pp. 22–26, Nov. 2025.

Issue

Vol. 4 No. 6 (2016): IJCSE Special Issue August Edition

Section

Review Article

License

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

Authors contributing to this journal agree to publish their articles under the Creative Commons Attribution 4.0 International License, allowing third parties to share their work (copy, distribute, transmit) and to adapt it, under the condition that the authors are given credit and that in the event of reuse or distribution, the terms of this license are made clear.