Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic

Authors

  • Nandhini M Electronics and Communication Engineering, Anna University, Coimbatore, India
  • Muralidharan V Electronics and Communication Engineering, Anna University, Coimbatore, India
  • Varatharaj M Electronics and Communication Engineering, Anna University, Coimbatore, India

Keywords:

Differential Power Analysis (DPA), Dual-Rail Logic, Security, Reverse Logic, Three-Phase Dual-Rail Pre-Charge Logic (TDPL)

Abstract

To design a data flip-flop consistent with the three-phase dual-rail pre-charge logic (TDPL) family. TDPL is a differential power analysis (DPA) resistant dual-rail logic style whose power consumption is insensitive to unbalanced load conditions, based on a three phase operation where, in order to obtain a constant energy consumption and also reduce the power dissipation replacing the discharge and evaluation phase by pull up and pull down networks using Reverse Logic. A part of an encryption algorithm is used as case a study to prove the effectiveness of the proposed circuit. Simulation results in a 65 nm CMOS process show an improvement in the energy consumption and power consumption.

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Published

2014-04-30

How to Cite

[1]
Nandhini M, Muralidharan V, and Varatharaj M, “Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic”, Int. J. Comp. Sci. Eng., vol. 2, no. 4, pp. 131–135, Apr. 2014.

Issue

Vol. 2 No. 4 (2014): IJCSE April Edition

Section

Research Article

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