Isaivani M, Malathi V, Sakthivel E. An Effective Interlaced Separation Vedic Multiplier in FPGA Platform. Int. J. Comp. Sci. Eng. [Internet]. 2025 Nov. 18 [cited 2026 Feb. 2];6(11):120-3. Available from: https://ijcse.isroset.org/index.php/j/article/view/3626