MAITRA, Subhashis. Design and Simulation of Two – bit Multiplier Circuit using MGDI Technique. International Journal of Computer Sciences and Engineering, [S. l.], v. 7, n. 6, p. 56–61, 2019. DOI: 10.26438/ijcse/v7i6.5661. Disponível em: https://ijcse.isroset.org/index.php/j/article/view/6505. Acesso em: 1 feb. 2026.