ISAIVANI, M; MALATHI, V; SAKTHIVEL, E. An Effective Interlaced Separation Vedic Multiplier in FPGA Platform. International Journal of Computer Sciences and Engineering, [S. l.], v. 6, n. 11, p. 120–130, 2025. DOI: 10.26438/ijcse/v6i11.120130. Disponível em: https://ijcse.isroset.org/index.php/j/article/view/3626. Acesso em: 2 feb. 2026.