GOPI KRISHNA, P; SUBRAHMANYAM, KV; CHANDRA SEKHAR, S. Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach. International Journal of Computer Sciences and Engineering, [S. l.], v. 2, n. 10, p. 19–25, 2014. Disponível em: https://ijcse.isroset.org/index.php/j/article/view/272. Acesso em: 2 feb. 2026.