NANDHINI M; MURALIDHARAN V; VARATHARAJ M. Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic. International Journal of Computer Sciences and Engineering, [S. l.], v. 2, n. 4, p. 131–135, 2014. Disponível em: https://ijcse.isroset.org/index.php/j/article/view/114. Acesso em: 2 feb. 2026.