Review Paper on High Performance Integrated Circuit for Multiplier-less Finite Impulse Response - Jain, Kriti; Kaur, Navneet (International Journal of Computer Sciences and Engineering, 2019)
This paper presents efficient modified distributed arithmetic (MDA)-based approaches for low delay reconfigurable implementation of finite impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in ROM; and the ROM-based LUT is found to be costly for application specific integrated circuit (ASIC) implementation. Therefore, a shared-LUT design is proposed to realize the MDA computation. Instead of using separate registers to store the possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage.