A Novel Low Power Full Adder Using a Modified Domino Logic - Jassbi, Somayyeh jafarali; mousavi, moloud (International Journal of Computer Sciences and Engineering, 2025)
A low power and high speed Full adder circuit design using a new CMOS domino logic family is presented in this paper. The presented domino logic is based on Magnetic Tunnel Junction Elements (MTJ) in Gate Diffusion Input (GDI) Technique. Compared to static CMOS logic circuits, dynamic logic circuits are important as it provides better speed and has less transistor requirement. The proposed circuit has very low dynamic power consumption and less delay compared to the recently proposed circuit techniques for the dynamic logic styles. Moreover, it will be shown that the proposed circuit is extremely fault tolerant. The monte carlo simulation is performed to emphasis the fault tolerance of proposed full adder. The proposed full adder is simulated using standard 0.18 um CMOS technology.