An Effective Interlaced Separation Vedic Multiplier in FPGA Platform - Isaivani, M; Malathi, V; Sakthivel, E (International Journal of Computer Sciences and Engineering, 2025)
A Multiplier is one of the essential components in the embedded system and digital signal processing (DSP) applications like digital filtering, digital communications, digital image processing, and spectral analysis etc. Parallel multiplication concept was implemented earlier to achieve higher speed. But in order to design an effective multiplier, speed is not the only consideration, area and power also must be taken into account while designing a circuit. To achieve this, a new technique has been introduced here for fast multiplication of two numbers. Inputs are separated into partitions where one number is again separated by two and zeros are interlaced in each alternate partition. Then it is followed by component multipliers and adders to get the final product. Based on the application requirement, the component adders and component multipliers can be selected in order to balance area and speed. The proposed system is synthesized using Xilinx tool. Experimental results show that the proposed interlaced separation Vedic multiplier is faster and has greater power efficiency in Field Programmable Gate Array (FPGA) implementation