Efficient Simulation of SoC based on Design Checkpointing for Efficient Debugging - Nikhil, KM; Veena, MB (International Journal of Computer Sciences and Engineering, 2025)
As the complexity of SoC design increases, functional verification of full chip takes more time and to verify the complete functionality of the design, many test cases need to be run. Here the simulation of DUT (Design-under-Test) is an important step to perform functional verification, which may require hours or days together for simulation. This can significantly impact on overall development time and time-to-market. The ability to restore regressions from a previously saved state can reduce considerably the development and debug cycle, thereby enhancing the productivity. This paper details a tool based checkpoint methodology for efficient simulation of Industrial SoC designs. This simulation checkpoint technique can greatly impact on reducing the development and debug cycle. Instead of saving the entire simulation state, only essential state of the simulation can be saved and the regressions are restored from that saved point in more dynamic way. It also describes how to avoid initial setup phase (RESET Phase) which is common for all test cases. These Checkpoint-restore techniques have been implemented to speed-up simulation of register-transfer level models and its effect on applying it to industrial SOC designs. In this Proposed work the experimental results on Industrial designs reveals that reset step which consumes approximately 17 hrs. can be restored in 43 minutes, saving almost 16 hrs. of simulation time for each of the testcases.