Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog HDL - Gopal, D.Venu; Reddy, M. Mohan (International Journal of Computer Sciences and Engineering, 2014)
This project deals with the comparison of the VLSI design of the carry look-ahead adder (CLAA) based 32-bit unsigned integer multiplier and the VLSI design of the carry select adder (CSLA) based 32-bit unsigned integer multiplier. Both the VLSI design of multiplier multiplies two 32-bit unsigned integer values and gives a product term of 64-bit values. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation whereas in CSLA based multiplier also uses nearly the same delay time for multiplication operation the overall simulation can be observed by using model sim and the synthesis report can be given by using Xilinx ise.