Power Efficient for DPA Resistat Flip Flop Using TDPL Inverter in Reverse Logic - Nandhini M; Muralidharan V; Varatharaj M (International Journal of Computer Sciences and Engineering, 2014)
To design a data flip-flop consistent with the three-phase dual-rail pre-charge logic (TDPL) family. TDPL is a differential power analysis (DPA) resistant dual-rail logic style whose power consumption is insensitive to unbalanced load conditions, based on a three phase operation where, in order to obtain a constant energy consumption and also reduce the power dissipation replacing the discharge and evaluation phase by pull up and pull down networks using Reverse Logic. A part of an encryption algorithm is used as case a study to prove the effectiveness of the proposed circuit. Simulation results in a 65 nm CMOS process show an improvement in the energy consumption and power consumption.